As is well known, the continuous decrease of the dimensions of integrated devices in modern technologies implies several problems.
In particular, in the case of memory devices, the reduction of distances between the memory cells strengthens the electric interactions between the adjacent cells in the usual structures with cell matrixes.
The majority of elements of a non-volatile memory device are floating gate memory cells, and FIG. 1 shows a cell being schematically and globally indicated with 10. The cells 10 are realized on a semiconductor substrate 1 wherein a source region 2 and a drain region 3 are defined, as well as a body region 4 interposed between the source 2 and drain 3 regions, the substrate 1 being overlapped by a first dielectric layer 5, so called gate dielectric, by a first polysilicon layer, defining the floating gate 6, by a second dielectric layer 7, so called interpoly dielectric, and by a second polysilicon layer, defining the control gate 8.
An integrated structure of cells 10 thus made has several capacitive couplings due to the alternation of conductive and insulating layers.
These couplings further interest the matrix of cells as a whole where, in particular, the capacitive coupling between the floating gates of topologically adjacent cells inside the matrix itself is relevant.
The mutual capacitive coupling between adjacent memory cells implies an alteration of the threshold voltage of a cell under examination when the threshold values of the adjacent cells vary.
This alteration is mainly felt during the programming step by the cells next to the cell to be programmed, and the alteration is proportional to the total threshold excursion of the cell to be programmed.
In particular, during the step of programming a memory matrix, the floating gates of the cells under programming are all at a low potential value.
A given cell being taken into consideration, it is noted that, due to the above described capacitive coupling and during the programming step, on its floating gate the potential value is at least partially transferred from the floating gates of the adjacent cells.
This potential variation of the floating gate shows itself as an enhancement of the threshold value of the cell under examination, also in case the charge of its floating gate, i.e., the value of the stored state in the cell, has not been varied on purpose.
It is thus to be noted that the threshold enhancement effect also interests cells having been correctly programmed, which are, however, adjacent to a cell being programmed.
For Flash memory devices of the multilevel type, the above indicated problems may worsen since, besides a low threshold level and a high threshold level, there are also intermediate threshold levels, and thus the intervals between one threshold and the other are reduced and shifts of the threshold values of the cells may occur, which may lead to errors in the reading of the programmed memory device.
To limit the alteration phenomena, maintaining the threshold levels programmed in each cell unaltered, it would be necessary to avoid that the cell, after having reached the desired threshold value, can see successive programming of the cells capacitively coupled thereto. This, however, typically requires modifications on the specifications of the programming step, which implies the cancellation, for example, of the repeated programming of a package of adjacent cells, an operation called, in the jargon, “bit manipulation”.
Some methods are known for reducing these alteration phenomena and in particular the shifts of the threshold levels during the programming of a group of cells of the matrix.
In particular, as shown in FIG. 2, in the programming of a matrix of cells 35, defined by a plurality of word lines WL 32 intersected by a plurality of bit lines BL 33, the cells 35 subject to the effect of the floating gate capacitive coupling are those contained between two consecutive word lines WL 32, which share a same source diffusion 34, and contained in the bit lines BL 33 comprised between two consecutive metallization strips 36.
This package of cells is also called a buffer, and is globally indicated with B. The buffer B, according to the specifications, most often coincides with the minimum amount of data being simultaneously programmable by a user and non subjected to a “bit manipulation”.
In particular, FIG. 2 shows a multilevel matrix, in a specific way with 2 bits per cell, with a cell X, which must be programmed with the lowest distribution i.e., “10” and having three adjacent cells Y, Z, K which must be programmed at the highest distribution “01”.
A programming method of the known type provides to use, for each buffer B of the matrix, a first programming which occurs, by means of a pulse sequence programming and successive verifications. This pulse sequence is carried out step-wise with increases of the constant pulse width and an “accurate” pitch p1 suitable to allow a correct positioning of the cells with intermediate distribution, i.e. “10” and “00”.
This method provides, further to each programming pulse, an elementary verify operation of the values stored in each cell. This operation comprises a comparison between a first value detected by each cell of the buffer B by means of a sense amplifier, and a second value stored in a location of a RAM wherein the target values of the cells 35 in the buffer B are stored.
If from this comparison, the value detected overcomes or equals the value stored, i.e. the target value, the cell 35 is considered as positively verified and the target value is changed with a predetermined value, typically “11”, which, afterwards, excludes the cell from successive pulse programming operations and relative verify operation.
The method then provides a second programming of the cells of the buffer B always by means of a pulse sequence programming and successive verifications. In particular, this pulse sequence is carried out step-wise with increases of the constant pulse width and a “rough” pitch p2, greater than the pitch p1 of the pulse sequence of the first programming.
This allows positioning the cells with higher distribution, i.e. “01”, in a quick way.
The second programming is followed by second verify operations, however carried out with lower frequency, i.e. after a defined number of pulses.
The described method is, although efficient under several aspects, often too invasive: all the cells of the buffer B are subjected to the step of first programming. In fact, the first programming with “accurate” pitch p1 is carried out in an indiscriminate way on all the cells of the buffer B and the cells having been already correctly programmed are needlessly subjected to an enhancement of the threshold value. This implies an increase of the possible capacitive couplings on the floating gates of the cells being correctly positioned when the adjacent cells are programmed.
Further, through the second programming with “rough” pitch p2, the cells of the buffer B with higher threshold distribution are verified in a loose way and thus some cells may undergo an excessive enhancement of the threshold distribution and this may also imply capacitive couplings on the floating gates of the cells of the buffer B.
Finally, also the verify operation is particularly tricky, needing, for each buffer B, more elementary verify operations, which comprise the reading of the values stored in the cells of the buffer and the comparison with the corresponding values stored in the RAM, operations which prolong the programming times of the buffer B.